1. Field of the Invention
The present invention generally relates to general purpose digital data processing systems and more particularly relates to such systems which execute multiple programs.
2. Description of the Prior Art
It is now common in large scale data processing systems to permit software developers to treat real storage as virtual memory. This is a technique wherein all memory accesses by a specific user program are relative in nature. The major advantage of this approach is that memory management can be efficiently performed by the system at the time of program execution depending upon resource availability and requests from other users. This memory management appears transparent to the user. The 2200/600 system available from the assignee of the present invention, and incorporated herein by reference, is such a system employing virtual addressing.
U.S. Pat. No. 4,827,406 issued to Bischoff et al, shows one method of handling virtual addressing. It is currently most desirable to structure an architecture in which the software makes address references relative to an addressing environment which can be readily loaded along with the program and can be modified during program operation as necessary. The actual physical memory hardware must be addressed, of course, using an real rather than a relative address. To accomplish this, the virtual address is converted to an absolute address using a translation table. A typical translation scheme is shown in U.S. Pat. No. 4,827,400 issued to Dunwell et al.
Further convenience and performance enhancements occur by dividing the virtual address space into blocks and by paging the real address space. The system is thus enhanced by providing logical divisions for programming purposes while accessing main memory by a hardware efficient block size. The conversion hardware efficiently performs the required translations without subjecting the user to the resulting bookkeeping. As a result, the storage resources of the system are efficiently managed in real time without unnecessary concern by the users.
The registers which store the data permitting conversion from the virtual address of a software program to the real address used by the physical storage system are assumed to be unique to that software program. As different programs are loaded and run, the contents of these registers must be modified. Similarly, the contents of one or more of the registers may need to be modified during the operation of a given program to permit access to different pages of data. U.S. Pat. No. 4,862,349 issued to Foreman et al, shows a technique for user modification of control block data. However, care must be exercised to prevent one program from inadvertently impacting another, unrelated program. U.S. Pat. No. 4,835,677 issued to Sato et al, shows a typical hardware protection approach. Notification to multiple users of a General Purpose Register set is provided by the technique of U.S. Pat. No. 4,903,196 issued to Pomerene et al.
The most common opportunities for a change to the data registers providing virtual to absolute address translation are during interrupts which transition the processor from one state to another, and at the initiation of an application program after the partial or complete run of a different and unrelated application program. The assignee of the present invention has for some time provided systems wherein the executive and user states have dedicated registers to mitigate a portion of this problem. A less efficient approach may be found in U.S. Pat. No. 4,825,358 issued to Letwin. U.S. Pat. No. 4,853,849 issued to Bain, Jr. et al, shows an alternative technique for input/output transfers.
Most modern large scale data processing systems also employ some form of microprocessing and pipelining. U.S. Pat. No. 4,825,363 issued to Baumann et al, and U.S. Pat. No. 4,841,436 issued to Asano et al, show microprocessor based architectures. Saving the processing environment upon the occurrence of a microinterrupt produces a similar need. U.S. Pat. No. 4,890,221 issued to Gage and U.S. Pat. No. 4,939,640 issued to Bachman et al, show architectures wherein the environment is saved by storing all of the variables.